Summer Semester 2008/09
Summer Semester 2009/10
Summer Semester 2010/11
Summer Semester 2011/12
Synthesis of Programmable Logical Chips EZ2B200013
Course content:
1. Review of PLDs.
2. Introduction to VHDL.
3. Lexical elements.
4. Sequential and concurrent statements.
5. Subprograms and packages.
6. Structural and behavior description of design.
7. Hierarchical structures.
8. Finite state machines.
9. Timing control.
10.CAD tools for designing PLDs.
11.Design flow.
12.Embedded processors and reconfigurable computing.
Learning outcomes:
This course introduces the students to the architecture and structural design of PLDs in the way, which is appropriate for both programmers and hardware engineers.
(in Polish) Rodzaj przedmiotu
Course coordinators
Bibliography
a) basic references:
1.IEEE-SA Standards Board: IEEE Standard VHDL Language reference manual, ieeexplore.ieee.org/iel5/7180/19335/00893288.pdf, USA, 2000.
2.Łuba T.: Synteza układów cyfrowych, WKiŁ, Warszawa, 2004.
3.Mano M.M., Kime Ch.R.: Podstawy projektowania układów logicznych i komputerów, NT, Warszawa 2007.
4.Skahill K.: Język VHDL Projektowanie programowalnych układów logicznych, WNT, Warszawa, 2001.
b) supplementary references:
1.Altera Corp.: Introduction to the Quartus II Software, San Jose, http://www.altera.com. /literature/manual/intro_to_quartus2.pdf, 2007.
2.HARDI Electronics AB.: VHDL handbook, Lund, Sweden, www.hardi.com, info@hardi.com, 2000.
3.Kalisz J.: Język VHDL w praktyce, WKiŁ, Warszawa, 2002.